llvm-rtdyld-3.5(1)



LLVM-RTDYLD(1)                   User Commands                  LLVM-RTDYLD(1)

NAME
       llvm-rtdyld - manual page for llvm-rtdyld 3.5

DESCRIPTION
       OVERVIEW: llvm MC-JIT tool

       USAGE: llvm-rtdyld [options] <input file>

   OPTIONS:
       -aarch64-neon-syntax                             - Choose style of NEON
              code to emit from AArch64 backend:

       =generic
              -   Emit generic NEON assembly

       =apple -   Emit Apple-style NEON assembly

       -bounds-checking-single-trap                    - Use  one  trap  block
              per function

       -check=<string>                                  - File containing Run-
              timeDyld verifier checks.

       -cppfname=<function name>                       - Specify the  name  of
              the generated function

       -cppfor=<string>                                 -  Specify the name of
              the thing to generate

       -cppgen                                         - Choose what  kind  of
              output to generate

       =program
              -   Generate a complete program

       =module
              -   Generate a module definition

       =contents
              -   Generate contents of a module

       =function
              -   Generate a function definition

       =functions
              -   Generate all function definitions

       =inline
              -   Generate an inline function

       =variable
              -   Generate a variable definition

       =type  -   Generate a type definition

       -disable-spill-fusing                            -  Disable  fusing  of
              spill code into instructions

       -dylib=<string>                                 - Add library.

       -enable-load-pre                                -

       -enable-misched                                 -  Enable  the  machine
              instruction scheduling pass.

       -enable-objc-arc-opts                            -  enable/disable  all
              ARC Optimizations

       -enable-tbaa                                    -

       -entry=<string>                                 - Function to  call  as
              entry point.

       -exhaustive-register-search                     - Exhaustive Search for
              registers bypassing the depth and interference cutoffs  of  last
              chance recoloring

       -fatal-assembler-warnings                        - Consider warnings as
              error

       -help                                            -  Display   available
              options (-help-hidden for more)

       -internalize-public-api-file=<filename>          -  A  file  containing
              list of symbol names to preserve

       -internalize-public-api-list=<list>              -  A  list  of  symbol
              names to preserve

       -join-liveintervals                               -   Coalesce   copies
              (default=true)

       -limit-float-precision=<uint>                   -  Generate  low-preci-
              sion inline sequences for some float libcalls

       -mc-x86-disable-arith-relaxation                - Disable relaxation of
              arithmetic instruction for X86

       -mips16-constant-islands                        - MIPS: mips16 constant
              islands enable.

       -mips16-hard-float                               -  MIPS:  mips16  hard
              float enable.

       -mlsm                                            -  Enable  motion   of
              merged load and store

       -mno-ldc1-sdc1                                   - Expand double preci-
              sion loads and stores to their single precision counterparts

       -no-discriminators                              - Disable generation of
              discriminator information.

       -nvptx-sched4reg                                  -   NVPTX   Specific:
              schedule for register pressue

       -print-after-all                                - Print IR  after  each
              pass

       -print-before-all                                - Print IR before each
              pass

       -print-machineinstrs=<pass-name>                - Print machine instrs

       -regalloc                                       - Register allocator to
              use

       =default
              -   pick register allocator based on -O option

       =basic -   basic register allocator

       =fast  -   fast register allocator

       =greedy
              -   greedy register allocator

       =pbqp  -   PBQP register allocator

       -rng-seed=<seed>                                 -  Seed for the random
              number generator

       -sample-profile-max-propagate-iterations=<uint>  -  Maximum  number  of
              iterations  to  go  through  when  propagating sample block/edge
              weights through the CFG.

       -spiller                                         -  Spiller   to   use:
              (default: standard)

       =trivial
              -   trivial spiller

       =inline
              -   inline spiller

       -stackmap-version=<int>                          - Specify the stackmap
              encoding version (default = 1)

       -stats                                           -  Enable   statistics
              output from program (available with Asserts)

       -time-passes                                      -   Time  each  pass,
              printing elapsed time for each on exit

       -triple=<string>                                 -  Target  triple  for
              disassembler

              Action to perform:

       -execute                                      - Load, link, and execute
              the inputs.

       -printline                                    - Load, link,  and  print
              line information for each function.

       -verify                                        -  Load, link and verify
              the resulting memory image.

       -verify-debug-info                              -

       -verify-dom-info                                - Verify dominator info
              (time consuming)

       -verify-loop-info                                 -  Verify  loop  info
              (time consuming)

       -verify-regalloc                                - Verify during  regis-
              ter allocation

       -verify-region-info                              -  Verify  region info
              (time consuming)

       -verify-scev                                    -  Verify  ScalarEvolu-
              tion's backedge taken counts (slow)

       -version                                         -  Display the version
              of this program

       -x86-asm-syntax                                 - Choose style of  code
              to emit from X86 backend:

       =att   -   Emit AT&T-style assembly

       =intel -   Emit Intel-style assembly

SEE ALSO
       The  full documentation for llvm-rtdyld is maintained as a Texinfo man-
       ual.  If the info and llvm-rtdyld programs are  properly  installed  at
       your site, the command

              info llvm-rtdyld

       should give you access to the complete manual.

llvm-rtdyld 3.5                  October 2016                   LLVM-RTDYLD(1)

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